1. Field of the Invention
The present invention relates to an encoding and decoding (hereinafter referred to as “CODEC”) system. More particularly, the present invention relates to a CODEC system and method for performing on-the-fly error checking and correcting (ECC) to support a non-volatile memory.
2. Description of the Related Art
FIG. 1 illustrates a block diagram of a conventional CODEC system 10. The CODEC system 10 includes an error correction unit 11, a temporary memory 12, e.g., a static random access memory (SRAM), and a non-volatile memory 13, e.g., a flash memory.
FIG. 2 illustrates an encoding process of accessing the flash memory 13 to write input data thereon in the CODEC system 10 of FIG. 1. Referring to FIG. 2, when the temporary memory 12 stores the input data, the error correction unit 11 accesses the temporary memory 12 to read the stored data (S21). Next, the error correction unit 11 generates parity from the read data (S22) and accesses the temporary memory 12 to store the parity therein (S23). Next, the flash memory 13 reads the input data and the parity from the temporary memory 12, and stores them as non-volatile data (S24).
FIG. 3 illustrates a decoding process of accessing the flash memory 13 and reading the non-volatile data from the flash memory 13 in the CODEC system 10 of FIG. 1. Referring to FIG. 3, the temporary memory 12 reads and stores data and corresponding parity from the flash memory 13 (S31). Next, the error correction unit 11 accesses the temporary memory 12 to read the stored data (S32). Thereafter, the error correction unit 11 corrects an error in the data using the parity (S33), and accesses the temporary memory 12 and stores the corrected data as output data in the temporary memory 12 (S34).
The output data stored in the temporary memory 12 may be transmitted to and processed by a processor (not shown), and output as multimedia data to be provided to users.
If the CODEC system 10 is an MP3 player, the flash memory 13 may be a multi-level cell (MLC) type flash memory. In this case, it is known that an error may occur in a maximum of four symbols among 512 byte memory cells corresponding to one page. Here, a symbol may be 9 bits. The encoding and decoding processes illustrated in FIGS. 2 and 3 are required to correct the error. When the CODEC system 10 encodes one page, the error correction unit 11 requires 512-byte read access and 9-byte write access to store 9-byte parity in the temporary memory 12. When the CODEC system 10 decodes one page, the error correction unit 11 requires at least 521-byte read access to read 512-byte data and 9-byte parity from the temporary memory 12.
However, conventionally, even if there is no error in the data, read/write access to the temporary memory 12 to generate parity in the encoding process, and read access to the temporary memory 12 to correct the error in the decoding process are performed unnecessarily. This increases power consumption and degrades system performance.